The present invention relates to a frequency corrector circuit for correcting deviations in frequency generated by, for example, an oscillator circuit to adjust the frequency.
An LSI (Large-Scale Integration) circuitry may in general include a frequency generator comprising a quartz oscillator, a trimmer capacitor and another capacitor. In the frequency generator, the quartz oscillator is provided between the input and output ports of the LSI circuitry. The input port to the LSI circuitry is connected to one terminal of the quartz oscillator and one plate of the trimmer capacitor. The output port to the LSI circuitry is connected to the other port of the quartz oscillator and one plate of the other capacitor. The trimmer capacitor and the other capacitor have the other ends thereof connected in common to ground.
This circuit configuration is used as timepiece in, for example, a microcomputer. For the microcomputer, a quartz oscillator is used for generating for example 32.768 kHz. This frequency is divided by a frequency divider into a waveform of 1 kHz for use in displaying the second hand or the like of the timepiece. For the frequency divider, fifteen T-type flip-flops are used. Each of the flip-flops is adapted to supply its Q output as clock signals to the successive stage of flip-flop for frequency division to ultimately form 1 Hz frequency.
Meanwhile, the quartz oscillator used is subjected to frequency variations or inaccuracy in the order of xc2x130 ppm as manufacture tolerance. The trimmer capacitor is adapted to vary its capacitance for correcting the variations for adjusting the frequency. However, the trimmer capacitor is more expensive than routine capacitors. Moreover, in employing trimmer capacitors, frequency adjustment is required in the manufacture process. Even if the frequency is adjusted, frequency deviation or fluctuation occurs due to an ambient temperature, which may often be different from one when adjusting the oscillator circuit.
Japanese Laid-Open Patent Publication No. 152938/1993 discloses a data processor comprising a counter capable of varying its count with a programmed number, a ring counter generating its counter output as clock pulses, and a coincidence circuit for comparing the count from the ring counter with a preset value. The programmed number in the counter is changeable in response to the output from the coincidence circuit. The programmed number is an integer obtained on dividing clock frequency with a target frequency and then dividing the resulting value with the maximum count of the ring counter. Since this counter operates in response to a pre-fixed clock frequency, it is not possible to cope with frequency deviations caused from time to time by temperature changes or lapse of time.
Japanese Laid-Open Patent Publication No. 311190/1997 teaches a timepiece unit having an automatic error correcting function, in which timing errors are automatically corrected in order to cope with the lead and lag of the fundamental pulses. This timepiece unit includes a quartz oscillator, a fundamental pulse oscillator circuit, a correction value input circuit and a pulse corrector for increasing or decreasing the fundamental pulses based on errors in the fundamental pulses to correct the errors. The fundamental pulse oscillator circuit generates fundamental pulses with a period of one second.
The pulse corrector includes a correction value operating unit, a correction pulse generator and a modulator to increase or decrease the fundamental pulses of 1 Hz. This timepiece unit corrects the frequency-divided output. The timepiece unit may be used with advantage to accurately correct the time indicated by a timepiece circuit, or real time clock (RTC).
However, since the RTC circuit is not adapted to accurately correct the clock signals for RTC per se, the RTC circuit still suffers from errors. Thus, Japanese Laid-Open Patent Publication No. 183660/1999 teaches a portable information processing apparatus with a timepiece built-in adapted for setting precisely the clock signals for RTC to correct values to decrease processing volume for RTC time corrections. The portable information processing apparatus disclosed in the Japanese publication includes an oscillator for RTC 21, a comparator 25 and a memory 12 to provide for a stable frequency of the clock signals readily to improve the reliability of the information processing functions of the apparatus applied.
However, with these techniques, the components used are expensive, while it is still required to perform frequency correction during the manufacturing process. Moreover, if the frequency is corrected, it is not possible to follow up with frequency variations brought about by environmental changes.
It is an object of the present invention to provide a frequency corrector circuit with a simplified configuration for accurately correcting the clock signals of the oscillating frequency without adjusting the oscillator circuit.
In accordance with the present invention, a frequency correction circuit for correcting a deviation in frequency of a signal generated from a clock signal obtained from an oscillator circuit, which comprises an oscillator device for generating a reference clock signal, and first and second capacitive elements, each of which has one end connected across the oscillator device and another end grounded, comprises a clock frequency divider for frequency-dividing the clock signal into a desired frequency. The clock frequency divider comprises a plurality of counters connected in cascade, each of which frequency-divides the clock signal and supplies a frequency-divided output to successive one of the plurality of counters as a clock, and a correction controller for controlling the clock frequency divider. The clock frequency divider further comprises a count adjuster for adjusting timing of counting carried out in response to the clock signal to cancel an error contained in the clock signal. The correction controller comprises a time setting circuit for setting of first and second reference times and initializing the clock frequency divider, a time generator for calculating a generation time corresponding to a sum of the first reference time supplied from the time setting circuit and a time from the clock frequency divider, a time comparator for comparing the generation time with the second reference time, and a count controller operative in response to the time comparator for supplying the count adjuster with a control signal controlling the plurality of counters to delaying or hastening a timing of counting.
With the frequency correction circuit of the present invention, the timing is calculated by the time generator in the correction controller by summing a first reference time supplied from the time setting circuit to the time supplied from the clock frequency divider. The generation time is compared by the time comparator circuit to the second reference time and, based on the result of the comparison, the count adjuster is controlled by the count controller to adjust the timing to cancel an error contained in the clock signals to enable the desired frequency to be output from the frequency divider.
Thus, it is possible to produce a desired frequency form the clock frequency divider with deviations corrected. Since no costly trimmer capacitor is needed in the oscillator circuit, but addition of a simplified circuit suffices, it is possible to suppress the cost.